For realizing practical neuromorphic systems, parallel computation in synapse arrays is an essential requirement \cite{Ielmini_2018,Joshi_2020,Yao_2020}. To evaluate the potentials of the device for parallel computation with spike-dependent learning process, we prepared the multi-cells of the developed memristors acting as an artificial synapse, as shown in Figure 5a. The memristor cells were then trained for logic operators of OR and AND (see Figure 5b), and the consumed energy values for the training and computing processes were analyzed as shown in Figure S19. In training the system, the SRDP characteristics of the cell were used for high energy efficiency and a simple scheme (see Figure S20). For the learning processes of “OR” and “AND”,  the developed system consumed approximately 4.28 and 1.01 nJ, respectively. For each logic operation, a single layer consisting of two input neurons and one output neuron was connected by two synapses.  In the logic operators, two different binary inputs (V1 and V2) with the pulse width of 100 ns were used, and an output current (IOR for OR and IAND for AND) was checked for a logic output. For logic inputs, 0.2 V and 0.002 V were utilized for "1" and "0" respectively, and the measured output current was compared with a threshold current (Ith) of 9 μA to estimate the output value. When the output current was higher (or lower) than 9 μA, the logic output was determined as "1" (or "0"). The memristor cells were reliably operated as the logic operators, as shown in Figure 5c. The average operating energy for the “OR” and “AND” logic computing was about 241 fJ, which is superior to that in CMOS systems \cite{Kim_2022}. Furthermore, we prepared the synapse array consisting of the 15 different memristor cells to achieve the complex logic operations. To store the letters of "K", "N", "U", "A", and "I" in the synapse array according to American standard code for information interchange (ASCII) based on the octal numbers, each cell was utilized as a synaptic component with 9 different memory states. The spike-dependent learning processes for the letters (see Figure S21) were effectively performed by consuming about 8.49 nJ, and the computing operation for the stored letters was reliably achieved at a 0.2-V reading voltage with 100 ns, with about 149 fJ (see Figure 5d). This indicates that our memristor can be utilized as an artificial synapse for energy efficient hardware neural networks.
In general, the performances of the artificial neural networks can be evaluated through their recognition capability for several types of pattern images \cite{Feng_2021,Kim_2021a,Shrestha_2021}. To confirm the capability of the developed PVA-based memristor for constructing the complex neural network, we conducted the numerical simulation of SPICE for the handwritten digit pattern recognition based on a dataset of the Modified National Institute of Standards and Technology (MNIST) \cite{Kim_2019a,Wang_2020}, as shown in Figure 5e. In the simulation, 60000 images for learning and 10000 images for classifying tests were utilized, and the pixel of each image had 256 levels for grayscale. A neural network was simply composed of a single layer, and 784 and 10 neurons were set for the digit images of 28×28 pixels and the classes of the digit images, respectively. The input and output neurons were connected through a single flexible memristor device, as shown in Figure 5f. In the learning processes, the ideal weight distribution calculated in the software system for classifying the digit images for MNIST (see Figure 5g) was converted to the cell conductance in the device arrays. It should be noted that the conductance parameters of the device cell were obtained from the results in Figure 4h. Only positive weight values were utilized to facilely convert the synaptic weight to the device conductance. Figure 5h shows the conductance distribution of the memristor array after the learning processes for 50 epochs. The ideal synaptic weights consisting of analog memory states were effectively quantized to the 16 levels of the device conductance. For the process of the recognition tests, the 0.1-V input voltage with 100 ns was applied to each cell, and the output current values of bit lines were confirmed. In the neural network based on the developed memristor, the pattern recognition accuracy was about 92 % after training 50 epochs, which is highly close to that of the ideal software system (see Figure 5i).  In addition, when the current-sensing resistor of 1 mΩ was utilized, the developed hardware neural networks classified digit images by consuming about 255 pJ, which is greatly more efficient than that of the von Neumann counterparts \cite{Shrestha_2021}. This implies that the developed PVA-based memristor with biodegradability and mechanical flexibility can be used as a synaptic device in the energy efficient hardware neural networks with high integration density.  

Conclusion

In conclusion, we demonstrated a biodegradable and flexible polymer based memristor with optimized synaptic plasticity for the spike-dependent learning process. We explored the ECM phenomenon and the resultant CF growth in the pure PVA medium, and analyzed the resistive switching effect of the PVA based memristor. It was found that, in the PVA based memristors, the metallic CF growth and its stability were effectively tuned by the polymer Mw. The developed PVA based memristor was stably operated as a resistive switching memory device, and the multilevel conductance states were effectively achieved by tuning the applied voltage conditions including the CC and the amplitude. The PVA-based memristor prepared on the plastic substrate exhibited the high mechanical flexibility and endurance performances, which is important for practical wearable electronics. Additionally, the developed flexible memristor was also acted as a transient device with highly superior biodegradability due to the high water solubility of the PVA medium.  Moreover, the device showed the reliable synaptic characteristics and the applicability as an artificial synapse for the energy efficient neural networks. The simple and complex logic operators were effectively trained in the developed synapse arrays through the spike-dependent learning process with low energy consumption.  Furthermore, the intelligent system with high energy efficiency for recognizing the handwritten digits was effectively constructed by utilizing the developed device, and such system exhibited the high pattern recognition accuracy of about 92 % which is close to that of the ideal software neural network. This novel strategy of realizing a transient and flexible synaptic device with the spike-dependent operation would be a fundamental platform for developing eco-friendly smart wearable electronics which are linked to next-generation intelligent systems.  

Acknowledgements

S. O. and H. K. contributed equally to this work as the first author. This work was supported by the National Research Foundation of Korea (NRF) under grant funded by the Korea Government (MSIT) (2020R1F1A1075436). This research was supported by National R&D Program through the National Research Foundation of Korea (NRF) funded by Ministry of Science and ICT (2021M3F3A2A03017764). This research was supported by the BK21 FOUR project funded by the Ministry of Education, Korea (4199990113966). This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (Ministry of Science and ICT) (No. 2021R1C1C2012074). This work was also supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MIST) (NRF-2022R1C1C100923511).  

Conflict of interest

The authors declare no conflict of interest.

Supporting Information

Supporting Information is available from the Wiley Online Library or from the author.