Abstract
Single junction crystalline silicon (c-Si) solar cells are reaching their practical efficiency limit while perovskite/c-Si tandem solar cells have achieved efficiencies above the theoretical limit of single junction c-Si solar cells. Next to low-thermal budget silicon heterojunction architecture, high-thermal budget carrier-selective passivating contacts (CSPCs) based on polycrystalline-SiOx (poly-SiOx) also constitute a promising architecture for high efficiency perovskite/c-Si tandem solar cells. In this work, we present the development of c-Si bottom cells based on high-temperature poly-SiOx CSPCs and demonstrate novel high-efficiency four-terminal (4T) and two-terminal (2T) perovskite/c-Si tandem solar cells. First, we tuned the ultra-thin, thermally grown SiOx. Then we optimized the passivation properties of p-type and n-type doped poly-SiOx CSPCs. Here, we have optimized the p-type doped poly-SiOx CSPC on textured interfaces via a two-step annealing process. Finally, we integrated such bottom solar cells in both 4T and 2T tandems, achieving 28.1% and 23.2% conversion efficiency, respectively.
Introduction
Single junction c-Si solar cells are reaching their practical efficiency limit [1],[2]. One way to further increase the efficiency of solar cells based on c-Si is to deploy them as bottom device in tandem structures with a wide bandgap top device. Perovskite/c-Si tandem solar cells attract considerable attention in this regard [3]-[31] with certified conversion efficiencies so far up to 32.5% [32]. The two common tandem architectures are a monolithically integrated two-terminal (2T) tandem configuration, where the two devices are electrically connected via a tunnel recombination junction (TRJ), and a mechanically stacked four-terminal (4T) tandem configuration where the two devices are optically connected but electrically decoupled. The 2T tandem solar cell design has simple electrical connections but requires current matching between the two devices to reach optimal efficiency. It is thus sensitive to the daily variations of solar spectrum. The 4T tandem configuration does not require current matching between its component devices and so has fewer restrictions on the device optimizations. However, due to the devices being electrically decoupled, each of them has its own transport layers and additional encapsulation layers for optical coupling, which increases the overall parasitic absorption. The advantages and disadvantages of 2T and 4T tandem configurations have been explored before [33]-[36]. As bottom device, besides silicon heterojunction (SHJ) cells [3]-[7],[24]-[27], silicon solar cells based on high-thermal budget carrier-selective passivating contacts (CSPCs) have rarely been reported [8], [28]-[30]. Such CSPCs are so-called since they require high temperature fabrication steps, which can be up to 1100 °C. Poly-crystalline silicon (poly-Si) is an example of these high-thermal budget CSPCs and has enabled high efficiency single junction c-Si solar cells [37]-[41], concurrently yielding high quality surface passivation and charges transport. However, doped poly-Si exhibits a high free carrier absorption, which has turned the attention of researchers towards wide bandgap materials, such as polycrystalline-SiCx [42],[43] and polycrystalline-SiOx (poly-SiOx), which can be more transparent while ensuring similar conductivity with respect to poly-Si [44],[45]. Such CSPCs consist of doped poly-Si, alloyed with carbon or oxygen, which are deposited on an ultra-thin SiOx layer, prepared by a wet-chemical process (nitric acid oxidation of silicon, NAOS) [45], thermal oxidation [46], UV/O3 process [47], or low-temperature plasma oxidation [48]. The opto-electronic properties of poly-SiOx depend on the oxygen content [45],[49]. Poly-SiOx is a novel material which has been successfully employed in c-Si single junction solar cells [45],[49],[50] and, to the best of our knowledge, its long-wavelength optical potential in tandems has not been explored so far. As these CSPCs are compatible with high temperature production processes, they are appealing to the mainstream c-Si PV industry. In view of potential tandem efficiencies well above 30%, perovskite/c-Si tandem solar cells with bottom cells fabricated with high-thermal budget CSPCs can significantly reduce the levelized cost of electricity compared to single junction silicon photovoltaics [51].
Solar cells fabricated with poly-SiOx CSPCs on an ultra-thin tunnelling SiOx layer grown via NAOS process have exhibited active area efficiency of around 21% in a front/back contacted (FBC) architecture [50]. However, these cells were 2-cm2 wide and deployed thermally evaporated metal contacts. In this work, next to adopting screen printing for metallization and developing larger area devices (from 2 cm2 to 4 cm2), an ultra-thin SiOx layer prepared by thermal oxidation of the c-Si surface is used as tunnelling SiOx. As compared to tunnelling oxide grown via NAOS, thermal oxides are denser and less prone to blistering, have lesser bulk defects, provide better wafer chemical passivation [52] and is more stoichiometric resulting in higher thermal stability [53]. Other advantages of using a thermal oxide are (i) the controllability over the oxide thickness and its microstructures by changing the oxygen flow rate, temperature, and time, and (ii) the industrial applicability in state-of-the-art furnaces.
We optimized the passivation of both n-type and p-type doped poly-SiOx on the ultra-thin thermally grown SiOx especially because p-type poly-SiOxon textured surfaces has been a limiting factor in terms of passivation [43],[52],[54]. To this end, a two-step annealing process was used to improve the passivation quality of p-type poly-SiOx CSPCs on textured interfaces. Finally, we studied the integration of c-Si solar cells endowed with these optimized high-thermal budget CSPCs in perovskite/c-Si 4T and 2T tandem devices, achieving conversion efficiency of 28.07% and 23.18%, respectively.
Experimental details
Crystalline silicon (c-Si) solar cells
We used 4-inch n-type float zone (FZ) double-side polished (DSP) Topsil wafers (orientation: <100>, resistivity: 1 ~ 5 Ω cm, thickness: 280 ± 20 μm). For double-side textured (DST) solar cells, both sides of the wafers were textured in a tetramethylammonium hydroxide (TMAH) solution containing ALKA-TEX (GP-Solar-GmbH) as additive. For single-side textured (SST) solar cells, the front side was protected by a thick silicon dioxide (SiO2) layer deposited using plasma-enhanced chemical vapour deposition (PECVD). After partially texturing the wafer, the SiO2 layer was etched using a Buffered Hydrogen Fluoride (BHF (1:7)) solution. Subsequently, the samples were cleaned by dipping them in HNO3 (99%), to remove eventual organic contaminations, and then in HNO3 (69.5%, at 110 °C) to remove inorganic contaminations. The samples are then dipped in 0.55% HF solution to remove any native oxide layer before thermal oxidation to grow a thin tunnelling oxide layer. Here, after preliminarily investigating an optimal growth temperature (ultimately fixed at 675 °C), the time of the thermal oxidation process is optimized. Then, both the n-type and the p-type poly-SiOx passivating contacts are deposited on the thermal oxide with a dual-stack layer of 10-nm thick intrinsic a-Si layer using low-pressure chemical vapour deposition (LPCVD) process and 20-nm thick doped a-SiOx:H layer from PECVD process. Thus, the total thickness of the passivating contact hereby described will not overcome 30 nm. Because of that thickness, an additional TCO layer is needed for lateral transport of carriers. Also here, after an initial study on the optimal annealing temperature seeking for an eventual co-annealing temperature between the n-type and p-type doped layers, these samples were annealed at 950 °C between 5 and 15 minutes to crystallize the abovementioned films into poly-SiOx layers and drive in the dopants for both DST and SST cells. In this high temperature process, hydrogen effuses from the whole layer stack. Therefore, these cell precursors were hydrogenated by forming gas annealing (FGA) at 400 °C for 1 hour after being preliminarily capped with a 100-nm thick PECVD SiNx layer [55]. Upon the removal of the SiNx capping layer, indium tin oxide (ITO) layers were sputtered to ensure efficient (i) lateral carrier transport of charge carriers and (ii) optical performance at the front side as an anti-reflective coating (75 nm) and at the rear side as an optical buffer for the rear reflector (150 nm) [56]. As this step deteriorates the passivation quality [50],[57],[58], an additional annealing was executed in hydrogen for one hour at 400 °C. Finally, screen printing and curing for 30 minutes at 170 °C was used to realize low-temperature front and rear Ag-based metallic contacts. We have also fabricated a front side flat (rear side textured) c-Si solar cell that is deployed in 2T tandem devices (see Figure 1). The fabrication of such an architecture is described in more detail in Section 2.2. The current-voltage measurements of c-Si solar cells were performed using an AAA class Wacom WXS-90S-L2 solar simulator. The best SST and DST devices were certified at the CalTeC of the Institute for Solar Energy Research Hamelin (ISFH), Germany, which provided also the related external quantum efficiency (EQE) spectra (illumination in-between the front metal fingers). For passivation tests, symmetrical samples were fabricated with n-type or p-type doped poly-SiOx CSPCs on flat and textured c-Si wafers. A lifetime tester (Sinton WCT-120) was used to perform passivation measurements, such as implied open-circuit voltage (iVoc), on precursors in quasi-steady-state photoconductance (QSSPC) or transient photoconductance decay (transient PCD) mode [59],[60].
Perovskite/c-Si tandem solar cells
For 2T perovskite/ c-Si tandem solar cells, SST solar cells were fabricated with front side flat n-type poly-SiOx and rear side textured p-type poly-SiOx. This configuration of the bottom sub- cell is chosen to meet the requirements for depositing the perovskite top device in a p-i-n configuration. After high temperature annealing (900 °C for 15 minutes) and the abovementioned hydrogenation step, the SiNx capping layer was removed. This was followed by sputtering 30-nm (150-nm) thick ITO layer on the front (rear) side of the cell. Finally, a 500-nm thick Ag layer was deposited on the rear side of the cell using thermal evaporation. Atomic layer deposition (ALD), in combination with solution-processing, thermal evaporation, and sputtering were used to fabricate the perovskite top device. On the front, flat ITO layer of the bottom device, the perovskite top device comprised in a bottom-up sequence NiOx / 2-(9H -carbazol-9-yl)ethyl]phosphonic acid (2PACz) / perovskite (1.67 eV) / C60 / SnOx / ITO / MgF2. The front electrical contact was made of evaporated silver. The 8-nm thick NiOx layer was deposited on the ITO layer using thermal ALD [61],[62]. The deposition was done at a base pressure of 5 × 10−6mbar in a home-built reactor using nickel bis(N ,N ’-di-tert-butylacetamidinate) (Ni(tBu-MeAMD)2) as nickel precursor and water as the co-reactant. The precursor bubbler was maintained at 90 °C and an Ar flow was used for bubbling. The substrate temperature approached 150 °C during the deposition. Subsequent solution-processed and evaporated layers were processed in an inert atmosphere. 2PACz (TCI, 98%, dissolved 0.3 mg/ml in ethanol) was deposited by spin-coating at 3000 rpm for 30 s followed by annealing the substrate at 100 °C for 10 minutes [63]. The perovskite precursor solution was prepared by mixing 936 µl PbI2 (TCI, >99.99%, 691.5 mg/ml in DMF:DMSO 4:1) with formamidinium iodide (FAI, Greatcell Solar Materials) (199.9 mg)and 936 µl PbBr2 (TCI, > 99%, 550.5 mg/ml in DMF:DMSO 4:1) with methylammonium bromide (MABr, Greatcell Solar Materials) (133.1 mg), followed by mixing the FAPbI3 and MAPbBr3 solutions in a 79:21 (v/v) ratio and adding 5 vol.% CsI (Sigma Aldrich, 99.999%, dissolved 389.7 mg/ml in DMSO) and 5 vol.% KI (Alfa Aesar, 99.998%, dissolved 249.0 mg/ml in DMF:DMSO 4:1). The precursor was spin-coated at 4000 rpm (5 s to reach 4000 rpm) for 35 s; at 25 s from the start of spin-coating, 300 µl anisole was cast onto the substrate leading to perovskite crystallization. The substrate was then placed on a hot-plate and the film was annealed at 100 °C for 30 minutes. Following the substrate cooling down, choline chloride (Sigma Aldrich, >99%, 1 mg/mL in 2-propanol) was dynamically spin-coated at 4000 rpm for 35 s followed by thermal annealing at 100 °C for 30 minutes. Then, C60 (10 nm) was deposited by thermal evaporation at a rate of 0.5 Å/s. Following that, spatial atomic layer deposition (s-ALD) was used to deposit a SnO2 (20 nm) buffer layer [64]. Tetrakis(dimethylamino)tin(IV) was used as tin precursor and water as the co-reactant. A nitrogen curtain was used to isolate the two half-reaction steps. A 180-nm thick ITO layer was deposited using RF sputtering process at a rate of 0.3 Å/s. Finally, a 100-nm thick Ag perimeter contact, and a 120-nm thick MgF2 anti-reflective coating were thermally evaporated to complete the tandem device. More information about this solar cell stack can be found in [65]. Schematic sketches of single junction solar cells combined with perovskite solar cells in 4T and 2T tandem devices are reported in Figure 1.
Current density – voltage (J–V) scans of the 2T perovskite/c-Si tandem solar cells were done using a tungsten-halogen illumination source filtered by a UV filter (Schott GG385) and a daylight filter (Hoya LB120) with intensity adjusted to 100 mW/cm2. A 1 cm2 shadow mask was used. The solar cells were operated under reverse or forward sweeps (between + 2.0 V and – 0.5 V for tandem solar cells) at a rate of 0.25 V/s using a Keithley 2400 source meter. The EQE measurements of the 2T perovskite/c-Si tandem solar cells were performed using a modulated monochromatic probe light (Philips focusline, 50 W) through a 1 mm radius aperture. The response was recorded and converted to the EQE using a calibrated silicon reference cell. Light- and voltage-biasing was used to isolate the EQE of the individual devices; 530 nm (perovskite) or 940 nm (silicon) bias light and a forward bias close to the open-circuit voltage of the single-junction solar cell was used.
The single junction c-Si solar cells, described in Section 2.1, were combined with earlier processed and certified semi-transparent perovskite solar cells [66]-[69] to fabricate the 4T tandem devices. The efficiency of 4T tandem cells was determined by following the procedure described by Werner et al. [70]. Next to the conversion efficiency of our 4T tandem devices, another outcome of this procedure was the filtered EQE of the deployed bottom devices.