As described in Section 2.1, hydrogenation by FGA after SiN_x layer capping is performed on p-type and n-type doped CSPCs to reintroduce the hydrogen that effused after high temperature annealing. Figure 4 shows the comparison in passivation of p-type and n-type doped poly-SiO_x symmetric samples after thermal annealing and after hydrogenation. The optimum thermal oxidation and annealing conditions, as described in Figure 3, have been chosen for each type of CSPC. We observe that p-type and n-type doped poly-SiO_x CSPCs applied on DSP and DST symmetric samples, respectively, gave the same iV_oc of 690 mV after high-temperature annealing which improved to 710 mV after hydrogenation. Using the 2-step annealing technique, the symmetric p-type doped poly-SiO_x applied on DST wafer exhibited an iV_oc of 687 mV after hydrogenation. Applying the same 2-step annealing technique to symmetric n-type doped poly-SiO_x on DST wafer (including the thermally grown tunnelling SiO_x prepared at 675 °C for 3 minutes as in the p-type case), an iV_oc of 690 mV was found after hydrogenation, resulting in lower passivation quality than the single step annealing case. Here, as the intrinsic poly-Si layer resulting from the first annealing got denser [73], we speculate that the phosphorus doping atoms do not easily reach the tunnelling SiO_x/c-Si bulk interface to establish an effective electric field. In addition, as shown in Figure 3(b), the tunnelling SiO_x prepared at 675 °C for 3 minutes is not the best condition for the n-type doped poly-SiO_x on a textured surface. Still, this case is investigated (and later put forward in solar cell fabrication) to realize a neat flow chart in which both n-type and p-type doped poly-SiO_x layers essentially undergo the same thermal processes at the same time.