Virtual memory compliance refers to the extent to which the behaviour of the virtual memory subsystem adheres to the specifications outlined in the RISC-V architecture. It ensures that the behavior of virtual memory operations, particularly the manipulation of permission bits within page table entries, aligns accurately with the documented expectations and standards of the RISC-V architecture. We developed customized RISC-V assembly tests that systematically modify permission bits within page table entries. These tests are compiled using GNU toolchain and executed using the RISC-V assembly code on both the Spike and Sail simulators through the RISCOF framework, facilitating cross-platform analysis. By comparing the resulting log files from the two simulators, we discern any inconsistencies or variations in memory access behaviors. The findings of this investigation provide insights into the fidelity of RISC-V architecture specifications with respect to virtual memory operations. We generally worked with two level page table in which first level is named as level 1 and second level is named as level 0. These outcomes are synthesized into a comprehensive HTML report, offering an in-depth exploration of permission bit effects on virtual memory within varying privilege modes. This research enhances comprehension of virtual memory functionality in the RISC-V architecture. This study contributes to a more robust understanding of virtual memory behavior and engenders confidence in the modeling and simulation of such systems.

As computational demands continue to evolve in  the modern era, the choice of hardware architecture plays a  pivotal role in optimizing the performance of compute-intensive  applications. This research paper delves into the exploration  and comparison of three prominent hardware architectures:  x86, ARM, and RISC-V, within the context of compute-intensive  applications. The study begins with a comprehensive overview  of these architectures, highlighting their distinctive features,  and strengths. Subsequently, we investigate their suitability and  adaptability in diverse compute-intensive workloads. Our  analysis encompasses a wide spectrum of parameters, including  computational throughput, power efficiency, scalability, and  architectural flexibility. We scrutinize the architectural  intricacies that impact the execution of compute-intensive tasks,  shedding light on both the advantages and limitations of each  architecture. We used the gem5 simulator to compare these  Instruction Set Architectures (ISA). We run different  benchmarks on gem5 with different ISA and different  configurations and compare the result. Based on these results  we predict which architecture is better in which scenario. Gem5  is not a cycle accurate simulator but it’s a model accurate. In  conclusion, “Exploring Architectural Variations: x86, ARM,  and RISC-V in Compute-Intensive Applications” offers a  comprehensive insight into the nuances of hardware selection  for compute-intensive workloads. Our findings aid system  architects, researchers, and technology enthusiasts in making  informed decisions about the most suitable architectural choice  for their specific compute-intensive applications, ultimately  contributing to advancements in computational performance  and efficiency